Field
Embodiments of the present disclosure generally relate to methods of manufacturing a vertical type semiconductor device, and more particularly to methods of manufacturing a vertical type semiconductor device with stair-like structures for semiconductor manufacturing applications.
Description of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technology challenges for next generation very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of VLSI and ULSI interconnect technology have placed additional demands on processing capabilities. Reliable formation of gate structures on the substrate is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
A patterned mask, such as a photoresist layer, is commonly used in forming structures, such as gate structure, shallow trench isolation (STI), bite lines and the like, on a substrate by etching process. The patterned mask is conventionally fabricated by using a lithographic process to optically transfer a pattern having the desired critical dimensions to a layer of photoresist. The photoresist layer is then developed to remove undesired portion of the photoresist, thereby creating openings in the remaining photoresist.
In order to enable fabrication of next generation devices and structures, three dimensional (3D) stacking of semiconductor chips is often utilized to improve performance of the transistors. By arranging transistors in three dimensions instead of conventional two dimensions, multiple transistors may be placed in the integrated circuits (ICs) very close to each other. Three dimensional (3D) stacking of semiconductor chips reduces wire lengths and keeps wiring delay low. In manufacturing three dimensional (3D) stacking of semiconductor chips, stair-like structures are often utilized to allow multiple interconnection structures to be disposed thereon, forming high-density of vertical transistor devices.
When forming stair-like structures in a film stack disposed on a substrate, an etching process along with a photoresist trimming process are repeatedly performed to etch the film stack with sequentially trimmed photoresist layer as etching masks. In an exemplary embodiment depicted in FIG. 1A, a trimmed photoresist layer (not shown) may serve as an etching mask layer to transfer structures onto a film stack 120 disposed on a substrate 104 to form stair-like structures 110 on the substrate 104 for forming a semiconductor device 100. The film stack 120 typically includes alternating layers of layers 120a, 120b (shown as 120a1, 120b1, 120a2, 120b2, . . . , 120a5, 120b5), either conductive layers or insulating layers, as shown in FIG. 1B. During etching, the photoresist layer is sequentially trimmed to different dimensions while serving as an etch mask to form stair-like structures 110 having different widths.
During manufacturing of the stair-like structures 110 on the substrate 104, each stair formed in the stair-like structures 110 has its intended width to allow channels 125 to be formed thereon, as sown in FIGS. 1A and 1B. In some embodiment where a higher device performance is required, different materials of the alternating layers 120a, 120b may be tested or tried. For example, when a higher electric mobility of the device performance is required, a metal conductive material is often utilized in the stair-like structures 110. In one example, a second layer 120b (shown as 120b1, . . . , 120b5 in FIG. 1B) of the alternating layers 120a, 120b may be removed from the stair-like structures 110 and replaced with a metal containing layer 150, as depicted in FIG. 1C, to improve the electrical performance of the device 100. However, when removing the original second layer 120b (shown as 120b1, . . . , 120b5 in FIG. 1B) from the stair-like structures 110 to replace or insert with the metal containing layer 150, as depicted in FIG. 1C, residuals and/or surface roughness 152 are often created at the interface 130 between the metal containing layer 150 and the original first layer 120a (shown as 120a1, . . . , 120a5 in FIGS. 1B and 1C), thus creating poor electrical contact at the interface 130, eventually leading to device failure or electrical performance degradation.
Thus, there is a need for improved methods and apparatus for forming stair-like structures with accurate profiles and dimension control for three dimensional (3D) stacking of semiconductor devices.